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////                                                              ////
////  CFIORead.v                                                  ////
////                                                              ////
////  This file is part of the "Pico E12" project                 ////
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//// Copyright (C) 2005, Picocomputing, Inc.                      ////
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////////////////////////////////////////////////////////////////////JF

`timescale 10ns / 1ns

//This module handles IO Read decoding. There are really no timing constraints required for this signal

module CFIORead(CFClock, CardEnabled, OE, WE, IORD, IOWR, REG, IOReadLatch, IORead, IOReadHold);

input CFClock;                                                        //200 MHz Free Running Oscillator
input CardEnabled;                                                    //Card Enable Signal
input OE;                                                             //IO Read
input WE;                                                             //IO Write
input IORD;                                                           //I/O Read
input IOWR;                                                           //I/O Write
input REG;                                                            //Attribute IO Access

output IOReadLatch;                                                   //Fast IO Read Latching Signal
output IORead;                                                        //Delayed Common IO Read
output IOReadHold;                                                    //IO Read Hold (Until Card Disconnect)

wire CFClock;
wire CardEnabled;
wire OE;
wire WE;
wire IORD;
wire IOWR;
wire REG;

wire IOReadLatch;
wire IORead;
wire IOReadHold;

wire RawIORead;
wire IOReadHoldLatchClear;
                                                                      //Asynchronous Decoding Logic
assign RawIORead = (CardEnabled) && (OE) && (WE) && (~IORD) && (IOWR) && (~REG);
assign IOReadLatch = (RawIORead);

                                                                      //Instantating this latch aviods HDL Warnings
																							 //The clear circutry was added for some Dell laptops that don't de-assert CE (ever)
LDCE IOReadHoldLatch(.Q(IOReadHold), .CLR(IOReadHoldLatchClear || ~CardEnabled), .D(1'b1), .G(IOReadLatch), .GE(~IOReadHold));
PulseGen IOReadHoldLatchClearPulse(.Clock(CFClock), .In(~IORead), .Out(IOReadHoldLatchClear));

//synthesis attribute init of IOReadHoldLatch is 0;
                                                                      //Delay Lines
RisingAndFallingDelay IOReadDelay(.Clock(CFClock), .In(RawIORead), .Out(IORead));

endmodule